1. Field of Invention
The present invention relates to processing high-speed digital signals and, in particular but not exclusively, to processing high-speed digital signals to recover clock and/or data signals from received high-speed signals.
2. Description of the Related Art
Recovery of a clock signal from a serial data stream requires that data is latched (sampled) on both the rising and falling clock edges, the data samples then being processed to produce a recovered clock signal.
When the frequency of the recovered clock signal (clock frequency) is high, bordering on the maximum speed of operation of the circuit elements making up the clock recovery circuitry, several design problems arise, as follows.
Firstly, the clock recovery circuitry will require signals which change at certain well-defined moments. It may be necessary to control the moment a control signal such as a reset signal changes to an accuracy of half a clock cycle or less. A standard reset circuit, previously considered for use in such clock recovery circuitry, is made up of two master-slave latches. With such a previously-considered reset circuit, however, it is found that at frequencies approaching the limit of the technology, it is not possible to guarantee in which half of the clock cycle a reset signal produced by the reset circuit will switch from one logical state to the other. This problem arises as the switching time of a master-slave latch varies due to manufacturing or processing tolerances, voltage margins and temperature variations (so-called PVT variation).
Secondly, the processing of the above-mentioned data samples is also problematic at very high clock frequencies. This processing is generally performed by one of two different methods. In the first method, the samples are examined during the second half of the clock cycle, and the result of the comparison is itself latched at the end of the clock cycle (i.e. the next rising clock edge). In the second method, at the end of the clock cycle (i.e. the next rising clock edge) the data samples are passed unprocessed from a first set of latches to a second set of latches. The data sample can then be examined during the next clock cycle. In this case, both samples are now aligned to the rising clock edge.
In both of the above methods the data sampled on the falling clock edge must be transferred from one latch to another latch within half a clock cycle. At frequencies bordering on the limit of the technology, this can be very difficult.
Thirdly, in clock recovery circuitry, it is also sometimes required to generate a circulating control sequence (e.g. 0111, 1011, 1101, 1110, 0111, . . . ) at the outputs of a control register. The control-register outputs are used to enable different respective latches, for example. In practice, however, the circulating control sequence may become corrupted, with the result that the enabling of the different latches is no longer performed correctly. For control registers having a small number of bits (e.g. four bits or less), the correctness of the actual individual control states (e.g. 0111, 1011, etc.) can be detected explicitly and checked. However, as the length of the control sequence increases (for example to 8 bits or more), the detection of the correct control states becomes more difficult. In particular, more gates are required to implement the circuitry for checking the correctness of the control states which inevitably leads to increased loads on the control-register outputs. At frequencies approaching the limit of the technology, such increased loading must be avoided if at all possible.
Fourthly, high-speed digital signal processing circuitry may also have a requirement to convert items of data in one form into items of data in another form. For example, it may be required to convert n-bit parallel data (n=8, for example) into a serial bit stream, for transmission at n times the frequency of the parallel data. Separate clock signals are generally provided for the parallel data and the serial data, the serial clock signal having a frequency of n times that of the parallel clock signal. A shift register or the like is used to store the parallel data temporarily before it is shifted out of the register as a serial bit stream, one bit per serial clock cycle. It is therefore necessary to be able to generate a transfer control signal at a suitable moment during each parallel clock cycle to bring about transfer of a new item of parallel data into the shift register. For example, if the parallel data is permitted to change at each rising edge of the parallel clock signal, a previously-considered approach is to use first and second series-connected latches, the first latch having the parallel clock signal as its data input and both latches being clocked by the serial clock signal. In this case, for n=8 and assuming that the parallel clock signal has a 50% mark-space ratio, the rising edge of clock cycle 4 of the serial clock signal coincides with the falling edge of the parallel clock signal. It is then expected that the first latch changes state, producing a detection signal, during clock cycle 5 of the serial clock signal as clock cycle 5 is the first cycle in which, at the rising edge of the cycle, the parallel clock signal has the low logic state. At the next serial clock cycle, clock cycle 6, the second latch changes state producing the transfer control signal, and a new item of parallel data is then transferred into the shift register from which the data would be shifted out, one bit per serial clock cycle, as the serial bit stream.
At very high frequencies approaching the limit of the technology, it is very difficult to control the relative phase of the serial clock signal with respect to that of the parallel clock signal (i.e. across all PVT and layout variations). As a result, the parallel clock may in practice have its falling edge just before, exactly at, or just after the rising edge of the serial clock in clock cycle 4. If it is before the rising edge, it is possible that the first latch would produce the detection signal during clock cycle 4 instead of clock cycle 5. In the worst case, the detection signal could become dynamically unstable, i.e. be produced randomly at either serial clock cycle 4 or 5. This would cause items of data to be transferred to the shift register at varying intervals of 7, 8 or 9 serial clock cycles.
Fifthly, in previously-considered data recovery circuitry, a clock which is recovered from the incoming serial data stream is used to latch the serial data stream. However, depending on the shape of the data eye in the serial data stream it may be desirable to use a clock which is offset from the recovered clock to perform the serial data latching. The simplest method for producing such an offset clock signal would be to delay the recovery clock signal using a delay element. However, this has inherent disadvantages, and in particular the delay is hard to control across process, voltage and temperature variations. Furthermore, such a delay element is difficult to control from outside the clock recovery circuitry and can only impose a delay (rather than an advance) relative to the recovered clock signal.